The selective epitaxial growth (SEG) of thin silicon or silicon-germanium films can be used to achieve a raised source/drain region in complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) devices utilizing silicon-on-insulator (SOI) technology.
However, epitaxial growth on the gate stack polysilicon results in a “mushroom-shaped” cap, due to unconstrained lateral growth during the epitaxial silicon growth process. When the lateral growth of this cap is excessive, a potential path for increased leakage current between the polysilicon of the gate structure and contacts landed on the source/drain area is created. In the worst case, such cap growth provides a potential for shorts between the polysilicon of the gate structure and the landed source/drain contacts, due to their close proximity.
Therefore, a method which overcomes the problems of excessive cap growth which is easily integrated into existing production facilities would be useful.
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